1. Field of the Invention
The present invention relates generally to methods for simultaneously applying protective layers to a plurality of semiconductor device components, or wafer-scale application of protective layers to semiconductor device components. More specifically, the present invention relates to methods for forming protective layers in which any delamination thereof or cracking therein that occurs during scribing, cutting, severing, or dicing of at least the protective layers is subsequently healed.
2. Background of Related Art
Due to the ever-decreasing dimensions of electronic devices, state-of-the-art electronic devices require components, including semiconductor devices, of ever-decreasing size and ever-increasing density.
One approach that has been taken to reduce the amount of area, or “real estate,” consumed by semiconductor devices has been to reduce the amount of packaging that is required therefor. Thus, so-called “chip-scale packages” (“CSPs”), which typically comprise semiconductor device packages with lateral (i.e., x-axis and y-axis) dimensions that are not much larger than, or are substantially the same size as, the corresponding lateral dimensions of the semiconductor dice thereof have been developed. In order to fabricate a semiconductor device package with such small dimensions, a minimal amount of protective, encapsulant material is typically used. Thus, the protective, encapsulant material may cover only the active surface of the semiconductor die. Additionally, a CSP may include a thin layer of protective, encapsulant material that covers the backside of the semiconductor die.
Such protective, encapsulant layers are typically formed at a “wafer scale,” meaning that they are formed prior to singulating, or dicing, semiconductor devices from a large-scale semiconductor substrate upon which multiple semiconductor devices have been fabricated. For example, a single layer of protective, encapsulant material may be disposed on a large-scale semiconductor substrate and spread over at least active surfaces of a plurality of the semiconductor devices that are carried by the semiconductor substrate. Such spreading may be effected by use of spin-on processes, use of a so-called “doctor blade,” spray-on techniques, screen printing, or the like. The protective encapsulant material is then cured or hardened to form a protective, encapsulant layer on surfaces of the semiconductor devices.
When a layer of protective, encapsulant material is formed over the entire surface of a large-scale semiconductor substrate, including on the “streets” that are located between adjacent semiconductor devices, it is necessary to cut through the protective, encapsulant layer to singulate, or dice, the semiconductor devices from one another. As such singulating or dicing is effected, the protective, encapsulant layer and the underlying substrate are subjected to mechanical stresses. These mechanical stresses cause the formation of microcracks in the protective, encapsulant layer, as well as delamination of regions of the protective, encapsulant layer from corresponding surfaces of the semiconductor device. Such cracks and delaminated regions may be problematic during subsequent stressing, testing, or use of the resulting CSP since the associated repeated heating and cooling of the semiconductor die thereof may further stress the protective, encapsulant layer, increasing the sizes of cracks and causing further delamination. In addition, as is well known in the art, the existence of cracks and delaminated regions in a protective encapsulant provides a pathway for potentially damaging contaminants through the protective encapsulant, and could ultimately result in failure of the packaged semiconductor die.
The inventors are not aware of CSPs that are substantially free of microcracks and delaminated regions or of a method by which such CSPs may be fabricated.